1. Technical Field
The present disclosure relates to the field of memory cells, and more specifically of antifuse memory cells, that is, of memory cells having a storage element, which is non-conductive in its initial state and becomes conductive after programming.
2. Description of the Related Art
FIG. 1 shows an example of an antifuse memory cell 10. In the upper portion of a P-type semiconductor substrate 1 are delimited active areas 2, each of which is surrounded with an insulating ring 3. Insulating ring 3 is for example of the type currently called STI (Shallow Trench Insulation) in the art. The antifuse memory element 10 and its control elements are formed in each active area. The actual memory element 10 is formed of a very thin insulating layer 7 and a conductive pad 9 on the insulating layer 7. Insulating layer 7 is formed above a portion of the active area or P-type well 2. Two N-channel access transistors are formed in the active area to connect the region arranged under thin insulator 7 to a terminal called BL, which generally corresponds to a bit line terminal. First transistor 11, used for transfer, comprises an insulated gate 13 formed above the substrate between drain and source regions 14 and 15. Second transistor 21, used for reading, comprises an insulated gate 23 between drain and source regions 15 and 24. Region 24 is covered with a pad 25 connected to terminal BL.
A metallization 27 coupled with a P+ region 29 formed in substrate 1 outside of the active areas has also been shown. Metallization 27 is connected to a generally grounded terminal BULK.
The memory cell has one or the other of two states according to whether insulator 7 effectively insulates conductor 9 from the substrate or to whether this insulator is made conductive by the flowing of a strong programming current. This programming current results from a programming voltage applied between a terminal HV connected to conductive layer 9 and terminal BL while transistors 11 and 21 are set to the on state.
FIG. 2 illustrates current IHV in the antifuse during the programming phase. First, during a time T1, which corresponds to the breakdown phase of the antifuse, the current varies slowly. Then, from the end of time T1, current IHV increases abruptly, and then remains substantially constant due to the current saturation of access transistors 11 and 21.
The performed tests show that time T1 is very variable, for example within a range from 100 ns to 10 μs, from one antifuse to another of a same wafer and for antifuse devices of different wafer batches, even for theoretically identical antifuses. Thus, in practice, many tests are performed and a time at least equal to the longest programming time detected during the tests is selected as the programming time. It can further be observed that the resistivity of antifuses programmed in this manner does not have a minimum and constant value.